Field effect transistor having two-dimensionally distributed field effect transistor cells

ABSTRACT

A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.

TECHNICAL FIELD

This disclosure relates generally to Field Effect Transistors (FETs) andmore particularly to improved layouts for such FETs.

BACKGROUND

As is known in the art, Field Effect Transistors (FETs) having a lineararray of a plurality of FET cells are used in many applications. Eachone of the FET cells has a source, a drain and a gate between the sourceand the drain to control a flow of carriers along a channel between thesource and drain. It should also be understood the source and drain maybe reversed in any electrical circuit application; with, in eithercircuit application, the gate controlling the flow of carriers between asource and a drain.

As is also known in the art, in some FETs, the gates are parallelfinger-like gates interconnected to a common gate contact on the topsurface of a substrate. Likewise, the individual drains connected to acommon drain contact electrode and the sources are connected to a commonsource contact using the air bridges over the gate fingers and overeither the drains, or over the sources, and with the air bridgesconnected at their ends to a common drain, or source, contact (notshown) on the bottom surface of the substrate with conductive viaspassing vertically through the substrate between the ends of the airbridge and the contact on the bottom surface. One such FET with the airbridges over the drains is shown in FIG. 1. Generally, many of these areFET cells are stacked together in a linear array in the output stage ofa power amp Monolithic Microwave Integrated Circuit (MMIC), as shown inFIG. 2A. The linear stacking of these FET cells determines the linear Ldimension size of the MMIC.

SUMMARY

In accordance with the present disclosure, a Field Effect Transistor(FET) is provided having: a plurality of FET cells having a plurality ofsource pads, a plurality of drain pads, and a plurality of gateelectrodes disposed on a surface of a substrate; each one of the FETcells having a corresponding one of the gate electrodes disposed betweenone of the source pads and one of the drain pads; a gate contactconnected to the gate electrodes of each one of the FET cells; a draincontact connected to the drain pad of each one of the FET cells; and asource contact connected to source pad of each one of the FET cells. Thecells are disposed on a surface in a two-dimensional array.

The inventors have recognized that the linear arrangement of the FETcells creates ‘bunching’ of thermal dissipation and creates high channeltemperatures in the FET. The inventors solve this problem by disposingthe cells in a two-dimensional array.

In one embodiment, FET cells are disposed in a U-shaped arrangement.

In one embodiment, one portion of the cells is disposed along a line andanother portion of the cells is disposed along an intersecting line.

In one embodiment, Field Effect Transistor (FET) is provided having: aplurality of finger-like gate electrodes electrically interconnected tosuccessively points along an edge of a common gate contact, a firstportion of the finger-like gate electrodes extending along to a verticaldirection and a second portion extending along a direction intersectingthe vertical direction.

In one embodiment, the direction intersecting the vertical direction isa horizontal direction.

In one embodiment, a third portion of a plurality of finger-like gateelectrodes; the first portion and the second portion being connected toopposite edges of the common gate contact.

In one embodiment, a third portion of a plurality of finger-like gateelectrodes electrically interconnected to successively points along thecommon gate contact and extending along the vertical direction; thefirst portion being connected to points along one portion of the edge ofthe common gate contact and the second portion being connected to pointsalong an opposite portion of the edge of the common gate contact.

With such an arrangement, the PET cells of the FET are arranged in threesections where the FET gates are aligned vertically, e.g., along avertical or y-dimension, in two sections and horizontally in onesection. By creating these three sections, the heat generated has moreunshared surface area over which to spread and thus dissipate. Thelayout optimizes phase matching in the gate and drain fingers whichmaximizes power and efficiency. Each FET cell needs to be typicallywithin 10 degrees in insertion phase from gain input to drain output tomaximize power. The power is maximized with no additional DC currenttherefore increasing efficiency as well. The gain is also maximized bydecreasing the source inductance. The total source inductance is definedby the vias to ground and the interconnecting metal on the top of thesubstrate. In a traditional air bridge, the vertical conductive vias atthe ends of the air bridge provide only two vias; here, for example, inthe U-shaped embodiment, there are four vias which greatly reducesoverall source inductance of the FET. In addition, the cost of the MMICis reduced because this layout allows for a smaller vertical dimensionand smaller overall semi-conductor material. The use of a combination ofhorizontal and vertical extending gates provides a FET with threeseparate sections all tied to a low source inductance.

The details of one or more embodiments of the disclosure are set forthin the accompanying drawings and the description below. Other features,objects, and advantages of the disclosure will be apparent from thedescription and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

FIG. 1 is a top view of a Field Effect Transistor (FET) according to thePRIOR ART;

FIG. 2A is a top view of a plan view of a linear array of here eight,FETs of FIG. 1 according to the PRIOR ART:

FIG. 2B shows the heat signature or spatial position of heat generatedby each on the eight FETS in the linear array of FIG. 2A according tothe PRIOR ART.

FIG. 3A is a plan view of a Field Effect Transistor (FET) according tothe disclosure;

FIG. 3B is a cross sectional sketch of a portion of the FET of FIG. 3A,such cross section being taken along line 3B-3B of FIG. 3A according tothe disclosure;

FIG. 3C is an prospective view of the FET of FIG. 3A according to thedisclosure;

FIG. 4A is a top view of a linear array of, here eight, FETs of FIG. 1according to the disclosure; and

FIG. 4B shows the heat signature or spatial position of each of heatgenerated by each on the eight FETS in the linear array of FIG. 4Aaccording to the disclosure.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Referring now to FIGS. 3A-3C, a Field Effect Transistor (FET) 10 isshown to a plurality of, here twelve, FET cells 12 ₁-12 ₁₂, each one ofthe FET cells 12 ₁-12 ₁₂ having: a source S; a drain D; and a gateG₁-G₁₂, respectively, each gate G₁-G₁₂ here an elongated, finger-likegate, being disposed between the source S and the drain D to control aflow of carriers along a channel between the source S and drain D; FETcells 12 ₁-12 ₄ being shown on FIG. 3B. Here, the PET 10 is formed usingphoto-lithographic chemical etching processing. More particularly, eachone of the FET cells 12 ₁-12 ₁₂ has, on an upper, planar surface 13 of asemiconductor substrate 15, here for example a substrate having galliumnitride (GaN), a corresponding one of the twelve gate electrodes G₁-G₁₂,respectively, in Schottky contact with the surface 13 of thesemiconductor substrate 15, as shown in FIG. 3k The FET 10 includes: sixdrain pads 20 ₁-20 ₆ in ohmic contact with the surface 13 of thesemiconductor substrate 15; and seven source pads 22 ₁-22 ₇ in ohmiccontact with the surface 13 of the semiconductor substrate 15, as shownin FIG. 3A. It is noted that each gate finger G₁-G₁₂ shares a drain (D)provided by one of the drain pads 20 ₁-20 ₆ and a source (S) provided byan adjacent one of the source pads 22 ₁-22 ₇. Thus, while source pad 22₁ provides the source (S) for FET cell 12 ₁, source pad 22 ₂ providesthe source (S) for both FET cells 12 ₂ and 12 ₃; source pad 22 ₃provides the source (S) for both FET cells 12 ₄ and 12 ₅; source pad 22₄ provides the source (S) for both FET cells 12 ₆ and 12 ₇; source pad22 ₅ provides the source (S) both for FET cells 12 ₈ and 12 ₉; sourcepad 22 ₆ provides the source (S) for both FET cells 12 ₁₀ and 12 ₁₁;source pad 22 ₇ provides the source (S) for FET cell 12 ₁₂. Likewise,drain pad 20 ₁ provides the drain (D) for both FET cells 12 ₁ and 12 ₂;drain pad 20 ₂ provides the drain (D) for both FET cells 12 ₃ and 12 ₄;drain pad 20 ₃ provides the drain (D) for both FET cells 12 ₅ and 12 ₆;drain pad 20 ₄ provides the drain (D) for both FET cells 12 ₇ and 12 ₈;drain pad 20 ₅ provides the drain (D) for FET cells 12 ₉ and 12 ₁₀;drain pad 20 ₆ provides the drain (D) for FET cells 12 ₁₁ and 12 ₁₂.Thus, one of the twelve gates G₁-G₁₂ is disposed between a source (S)and a drain (D) of each one of the FET cells 12 ₁₁ and 12 ₁₂. Thus, gateG1 is disposed between source pad 22 ₁ and drain pad 20 ₁; gate G2 isdisposed between source pad 22 ₂ and drain pad 20 ₁; gate G3 is disposedbetween source pad 22 ₂ and drain pad 20 ₂; gate G4 is disposed betweensource pad 22 ₃ and drain pad 20 ₂; gate G5 is disposed between sourcepad 22 ₃ and drain pad 20 ₃; gate G6 is disposed between source pad 22 ₄and drain pad 20 ₃; gate G7 is disposed between source pad 22 ₄ anddrain pad 20 ₄; gate G8 is disposed between source pad 22 ₅ and drainpad 20 ₄; gate G9 is disposed between source pad 22 ₅ and drain pad 20₅; gate G10 is disposed between source pad 22 ₆ and drain pad 20 ₅; gateG11 is disposed between source pad 22 ₆ and drain pad 20 ₆; and gate G12is disposed between source pad 22 ₇ and drain pad 20 ₆, as shown in FIG.3A.

The FET 10 includes: a gate contact 14 connected to the gates G1-G12 ofeach one of the FET cells 12 ₁-12 ₁₂; a drain contact 16 connected toeach one of the drain pads 20 ₁-20 ₆, as shown in FIG. 3A. The sourcepads 22 ₁-22 ₇ are electrically interconnected by air bridges 26 shownmore clearly in FIG. 3C. A source contact 18 (FIGS. 3A-3C) is disposedon the bottom of the substrate 15 (FIG. 3B) and is connected to sourcepads 22 ₁, 22 ₃, 22 ₅ and 22 ₇ by conductive vias 28 passing through thesubstrate 15, as shown in FIGS. 3A-3C.

More particularly, and referring also to FIG. 3B, the cells 14 aredisposed on the upper surface 13 of the substrate 15 in atwo-dimensional array in an X-Y plane (FIGS. 3A and 3B). The finger-likegate electrodes G1-G12 are electrically interconnected to successivelypoints, P, along an edge of the common gate contact 14. It is noted thata first portion 30 of the finger-like gate electrodes G1-G4 extend alongto a vertical direction or Y direction (FIG. 3A) and a second portion 32of the finger-like gate electrodes G5-G8 extending along a directionintersecting the vertical direction, here for example, a horizontal or Xdirection. It is noted that a third portion 34 of a plurality offinger-like gate electrodes G9-G12 extend along to a vertical directionor −Y direction (FIG. 3A) the first portion 30 and the third portion 34are connected to opposite edges of the common gate contact 14 and extendin opposite directions. Thus, here in this example, the FET 10 is aU-shaped FET 10.

Referring now to FIGS. 2A and 4A, it is noted that the verticaldimension (along the Y-axis) of an array of the eight FETs 10, eachhaving twelve FET cells,(FIG. 3A) with the FETs of the FIG. 1, the eightFETS 10 occupy less of the vertical (Y axis) dimension. It is also notedin comparing the heat signature of the array of eight FETs 10 of FIG.3A, with the heat signature of the array of FETs in FIG. 1 (FIG. 2B),with the array of the FETs 10 of FIG. 3A the heat is distributed in twodimensions (the X and Y directions, FIG. 4B) and therefore the heatgenerated has more unshared surface area over which to spread and thusdissipate.

A number of embodiments of the disclosure have been described.Nevertheless, it will be understood that various modifications may bemade without departing from the spirit and scope of the disclosure. Forexample, instead of a U-shaped FET cell, other shapes wherein the FETcells are distributed in two dimensions may be used, such as forexample, a V-shaped FET cell, a cup-shaped cell, a concave shaped cell,a parabolic shaped cell. Further, the source and drain may be reversedin any electrical circuit application; with, in either circuitapplication, the gate controlling the flow of carriers between a sourceand a drain. Accordingly, other embodiments are within the scope of thefollowing claims.

1. A Field Effect Transistor (FET), comprising: a plurality of FET cellshaving a plurality of source pads, a plurality of drain pads, and aplurality of gate electrodes disposed on a surface of a substrate; eachone of the FET cells having a corresponding one of the gate electrodesdisposed between one of the source pads and one of the drain pads; agate contact connected to the gate electrodes of each one of the FETcells, the plurality of gate electrodes being finger-like electrodeextending outwardly from the gate contact; a drain contact connected tothe drain pad of each one of the FET cells; a source contact connectedto source pad of each one of the FET cells; wherein the cells aredisposed on a surface in a two-dimensional array; wherein a firstportion of the FET cells have the gate electrodes thereof control a flowof carriers passing between the drain pads and the source pads of thefirst portion of the FET cells; wherein a second portion of the FETcells have the gate electrodes thereof control a flow of carrierspassing between the drain pads and the source pads of the second portionof the FET cells; and wherein the first portion of the gate electrodesextend along a first direction and a second portion of the gateelectrode extend along a second direction, the second directionintersecting the first direction.
 2. The Field Effect Transistor (FET)recited in claim 1 wherein the FET cells are disposed in a non-lineararray.
 3. The Field Effect Transistor (FET) recited in claim 1 whereinthe FET cells are disposed in U-shaped arrangement
 4. The Field EffectTransistor (FET) recited in claim 1 wherein one portion of the cells isdisposed along a line and another portion of the cells is disposed alongan intersecting line.
 5. A Field Effect Transistor (FET), comprising: aplurality of FET cells having a plurality of finger-like gateelectrodes, each one of the FET cells having a corresponding one of theplurality of finger-like gate electrodes disposed between a drain padand a source pad of such one of the FET cells; a common gate contact;and wherein the finger-like gate electrodes are interconnected to pointsdisposed successively along an edge of the common gate contact, a firstportion of the plurality of finger-like gate electrodes extendingoutwardly from the common gate contact along to a vertical direction anda second portion of the plurality of finger-like gate electrodesextending outwardly from the common gate contact along a directionintersecting the vertical direction.
 6. The Field Effect Transistor(FET) recited in claim 5 wherein the direction intersecting the verticaldirection is a horizontal direction.
 7. The Field Effect Transistorrecited in claim 5 wherein a third portion of a plurality of finger-likegate electrodes extend outwardly from the common gate contact; andwherein the first portion and the second portion are connected toopposite edges of the common gate contact.
 8. The Field EffectTransistor recited in claim 5 wherein a third portion of a plurality offinger-like gate electrodes is electrically interconnected tosuccessively points along the common gate contact and extend outwardlyfrom the common gate electrode along the vertical direction; the firstportion being connected to points along one portion of the edge of thecommon gate contact and the third portion being connected to pointsalong an opposite portion of the edge of the common gate contact.
 9. AField Effect Transistor (FET), comprising: a plurality of FET cellshaving a plurality of source pads, a plurality of drain pads, and aplurality of gate electrodes disposed on a surface of a substrate; eachone of the FET cells having a corresponding one of the gate electrodesdisposed between one of the source pads and one of the drain pads; agate contact connected to the gate electrodes of each one of the FETcells; a drain contact connected to the drain pad of each one of the FETcells; a source contact connected to source pad of each one of the FETcells; wherein a first portion of the FET cells have the gate electrodesthereof control a flow of carriers passing between the drain pads andthe source pads of the first portion of the FET cells along a firstdirection; wherein a second portion of the FET cells have the gateelectrodes thereof control a flow of carriers passing between the drainpads and the source pads of the second portion of the FET cells along asecond direction; and wherein the first direction intersects the firstdirection.